[U-Boot] No NAND device found!!! Freescale MPC8544+SAMSUNG 1GB Nand Flash , please help!

[duckycool]

http://www.nabble.com/file/p25455541/nand_error.bmp nand_error.bmp Hi all,
I can't do READID with nand_get_flash_type in the nand_base.c
What I get is an error "No NAND device found!!!"
My board is freescale mpc8544 with samsung K9K8G08U0A, the device is
supposed {NAND 1GiB 3,3V 8-bit", 0xD3, 0, 1024, 0, LP_OPTIONS} .

What I did is copy the nand.c from /board/tqc/tqm85xx/nand.c into
/board/freescale/mpc8544ds
Add #define CONFIG_CMD_NAND into MPC8544DS.h, setup TLB/LAW/BR/OR for nand
flash.
Add RAM array of upm into /board/.../nand.c.

When booting, I can get the chip select signal put low with scope.
Trace the code, it get both dev_id and tmp_id 0x000000ff.

Per the /driver/mtd/nand/nand_base.c , /driver/mtd/nand/fsl_upm.c , and
/board/.../nand.c ....
I break down the upm operation into the upm control(mamr, mar, IO_ADDR_R,
IO_ADDR_W)
And then, I tried the low level register control under CodeWarrior command
window, it's still failed.

As below: (CCSRBR = 0xe0000000 , nand_flash_base = 0xff000000)
change 0xe0005070 0x30000008 (OP=11, pattern_offset=8)
change 0xe0005068 0x90000000
change 0xff000000 0x0
change 0xe0005070 0x0
change 0xe0005070 0x30000010
change 0xe0005068 0x00000000
change 0xff000000 0x0
change 0xe0005070 0x0
change 0xe0005070 0x30000008
change 0xe0005068 0x00000000
change 0xff000000 0x0
change 0xe0005070 0x0
display 0xff000000

I don't know why?
Any MARCO I should add ?
Or any special operation should I add into nand_base.c ?
Please help, thank you.

[duckycool]

Hi all,
Correction, the nand flash is K9F8G08U0M.
Please help

Post by duckycool
http://www.nabble.com/file/p25455541/nand_error.bmp nand_error.bmp Hi all,
I can't do READID with nand_get_flash_type in the nand_base.c
What I get is an error "No NAND device found!!!"
My board is freescale mpc8544 with samsung K9K8G08U0A, the device is
supposed {NAND 1GiB 3,3V 8-bit", 0xD3, 0, 1024, 0, LP_OPTIONS} .
What I did is copy the nand.c from /board/tqc/tqm85xx/nand.c into
/board/freescale/mpc8544ds
Add #define CONFIG_CMD_NAND into MPC8544DS.h, setup TLB/LAW/BR/OR for
nand flash.
Add RAM array of upm into /board/.../nand.c.
When booting, I can get the chip select signal put low with scope.
Trace the code, it get both dev_id and tmp_id 0x000000ff.
Per the /driver/mtd/nand/nand_base.c , /driver/mtd/nand/fsl_upm.c , and
/board/.../nand.c ....
I break down the upm operation into the upm control(mamr, mar,
IO_ADDR_R, IO_ADDR_W)
And then, I tried the low level register control under CodeWarrior
command window, it's still failed.
As below: (CCSRBR = 0xe0000000 , nand_flash_base = 0xff000000)
change 0xe0005070 0x30000008 (OP=11, pattern_offset=8)
change 0xe0005068 0x90000000
change 0xff000000 0x0
change 0xe0005070 0x0
change 0xe0005070 0x30000010
change 0xe0005068 0x00000000
change 0xff000000 0x0
change 0xe0005070 0x0
change 0xe0005070 0x30000008
change 0xe0005068 0x00000000
change 0xff000000 0x0
change 0xe0005070 0x0
display 0xff000000
I don't know why?
Any MARCO I should add ?
Or any special operation should I add into nand_base.c ?
Please help, thank you.

[Bin Meng]

? Correction, the nand flash is K9F8G08U0M.

K9F8G08U0M is a 4KB page size NAND flash.
Freescale eLBC NAND flash controller does not support 4KB page size.

thanks
bmeng

[duckycool]

Hi,
I'm not using eLBC, but UPM of local bus controller of mpc8544.

Post by Bin Meng

? Correction, the nand flash is K9F8G08U0M.

K9F8G08U0M is a 4KB page size NAND flash.
Freescale eLBC NAND flash controller does not support 4KB page size.
thanks
bmeng
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[Anton Vorontsov]

Post by Bin Meng

? Correction, the nand flash is K9F8G08U0M.

K9F8G08U0M is a 4KB page size NAND flash.
Freescale eLBC NAND flash controller does not support 4KB page size.

MPC8544 doesn't have eLBC, so its LBC can't speak NAND directly,
only via UPM (user-programmable machine). And with UPM we can
support any NAND flashes.

As for the original problem, it could be anything: schematics (I assume
it's custom 8544 board), timings setup (OR/BR), or UPM array problem.

Unfortunately it's hard to debug these sort of things without logic
analyzer, so if you don't have one, I'd suggest to play
'trial & error' game.

Cc'ing Wolfgang Grandegger though, maybe he has better ideas.

[duckycool]

Hi Anton,
Thank you, I have done a lot trial and error but still in vain.
I'm using u-boot-2009.06-rc3.
This is my /board/freescale/mpc8544board/nand.c below, as to nand_base.c
and fsl_upm.c I didn't change change anything.

=========================== nand.c ====================================
/*
* Initialize UPM for NAND flash access.
*/
static void nand_upm_setup (volatile ccsr_lbc_t *lbc)
{
int i=0;

static uint UPMATable[] = {
0x0fffff00, 0x0ffcfc00, 0x0ffcfc00, 0xfffffc04,
0xfffffc01, 0xfffffc00, 0xfffffc00, 0xfffffc01,
0x0ffffc00, 0x0ffcfc80, 0x0ffdfc00, 0x0ffffc04,
0x0ffcfc00, 0x0ffdfc00, 0x0ffffc04, 0x0ffcfc00,
0x0ffdfc00, 0x0ffffc04, 0x0ffcfc00, 0x0ffdfc00,
0x0ffffc84, 0xfffffc00, 0xfffffc01, 0xfffffc01,
0xfffffc20, 0x0fe33c00, 0x0fa33c00, 0x0ff77c05,
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
0x0feffc80, 0x0faffc00, 0x0ffffc04, 0x0feffc00,
0x0faffc00, 0x0ffffc04, 0x0feffc00, 0x0faffc00,
0x0ffffc04, 0x0feffc00, 0x0faffc00, 0x0ffffc84,
0xfffffc01, 0xfffffc00, 0xfffffc00, 0xfffffc01,
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01
};

lbc->mamr = 0x10000000; //op=10

for(i=0;i<64;i++)
{
lbc->mdr = UPMATable[i];

printf("lbc->mdr is 0x%08x \n", lbc->mdr);

*(char *)(0xff000000) = 0x0; //dummy write
}
lbc->mamr = 0x00000000; //normal

while (lbc->mamr !=0x00000000); //wait MAMR finish writting
printf("ram array is done\n");

return;
}

static struct fsl_upm_nand fun = {
.width = 8,
.upm_cmd_offset = 0x08,
.upm_addr_offset = 0x10,
.upm_mar_chip_offset = CONFIG_SYS_NAND_CS_DIST,
.chip_offset = CONFIG_SYS_NAND_CS_DIST,
.chip_delay = NAND_BIG_DELAY_US, //per spec, 25 us
.wait_flags = FSL_UPM_WAIT_RUN_PATTERN | FSL_UPM_WAIT_WRITE_BUFFER,
};


int board_nand_init (struct nand_chip *nand)
{
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
debug("board_nand_init begin \n");

nand_upm_setup (lbc);
nand->options = NAND_SAMSUNG_LP_OPTIONS ;

fun.upm.io_addr = nand->IO_ADDR_R;
fun.upm.mxmr = (void __iomem *)&lbc->mamr;
fun.upm.mdr = (void __iomem *)&lbc->mdr;
fun.upm.mar = (void __iomem *)&lbc->mar;

debug("fun.upm.io_addr is 0x%08x \n", fun.upm.io_addr );
debug("fun.upm.mxmr is 0x%08x \n", fun.upm.mxmr );
debug("fun.upm.mdr is 0x%08x \n", fun.upm.mdr );
debug("fun.upm.mar is 0x%08x \n", fun.upm.mar );

return fsl_upm_nand_init (nand, &fun);
}

=======================================================================

Any hint ? Please help !
Thanks.

Post by Anton Vorontsov

Post by Bin Meng

? Correction, the nand flash is K9F8G08U0M.

K9F8G08U0M is a 4KB page size NAND flash.
Freescale eLBC NAND flash controller does not support 4KB page size.

MPC8544 doesn't have eLBC, so its LBC can't speak NAND directly,
only via UPM (user-programmable machine). And with UPM we can
support any NAND flashes.
As for the original problem, it could be anything: schematics (I assume
it's custom 8544 board), timings setup (OR/BR), or UPM array problem.
Unfortunately it's hard to debug these sort of things without logic
analyzer, so if you don't have one, I'd suggest to play
'trial & error' game.
Cc'ing Wolfgang Grandegger though, maybe he has better ideas.
--
Anton Vorontsov
email: cbouatmailru at gmail.com
irc://irc.freenode.net/bd2
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